IEEE Reliability Society Newsletter     Vol. 61, No. 1, February 2015

Table of Contents

Front page:

President's Message

From the Editor

Society News:

RS Banquet at RAMS: Lifetime Achievement and Engineer of the Year Awards

RS Banquet at RAMS: New ExCom Slate and AdCom Electees

Members & Chapters

Boston Chapter

Dallas Chapter

Arizona Chapter

RS Chapter Outreach: China

Meetings & Conferences

Call for Abstracts: 2015 ASTR Conference, Boston, MA

Announcing 2015 IRPS, Monterrey, CA

PHM-2015 Announced: Austin, TX

Call for Papers: 2015 QRS, Vancouver, Canada

Letters in Reliability

Revisiting Perception of Reliability: Uninteroperability in US Power Grid


Reliability Society Home

RS Newsletter Homepage

2015 IEEE International Reliability Physics Symposium (IRPS)

April 19-23 * Hyatt Regency Monterey Resort and Spa * Monterey, CA, USA

http://IRPS.ORG   Find us on Facebook  Join the IRPS LinkedIn Group   Follow IRPS on Twitter   IRPS on Instagram

Beautiful Monterey- a great place for a conference

Technical Program Committee Meeting Dec’14

IRPS15 conference has been finalized with 94 platform presentations, 14 invited talks, and 73 posters by a globally well-represented 156 technical program committee members and chairs. The opening keynotes will be given by Kaizad Mistry (Intel) and Brent Keeth (Micron) with details posted already on Facebook. The technical program will then commence with three parallel tracks; a listing of the accepted abstracts is posted with the program in review The conference has 15 technical areas which encompass the entire reliability area of semiconductors. Unique to this year’s conference is a focus on dielectric breakdown where we have created a new session with transistor breakdown and the backend dielectric presentations to encourage new thought.


We’ve mentioned previously IRPS is also the only comprehensive reliability conference covering the breadth of device reliability from time dependent dielectric breakdown testing and models to compound device reliability to interconnect electro-migration to soft error to electronic system reliability to process integration to chip-package interaction. The conference begins with two days of tutorials plus reliability year in review. Tutorials are divided into three tracks seven sessions with track categories technology, component, and system. The traditional front end and back end will be complimented by middle of line reliability. A few examples of new topics are self-heating effects, stats in reliability & returns analysis, system level design for reliability, and static random access memory wafer level reliability. The topic list along with instructor biography and abstract are on  This conference is ideal for industry professionals to both broaden and deepen their knowledge while networking with others whether just starting their career or a seasoned reliability veteran. It is also ideal for students to discover the exciting area of reliability engineering!

Pre-Conference Highlights

We want Reliability Society membership to know the selected presentations for highlight prior to the conference which were chosen by the technical program committee. The first is from the transistor reliability session by Kerber et al titled “Impact of RTN on stochastic BTI degradation in scaled Metal Gate / High-k CMOS technologies”. In this work, the authors propose that random telegraph noise (RTN) and negative bias temperature instability (NBTI) have different origins as RTN exhibits no change after NBTI stress. The second highlight is from the circuit aging and reliability session from Lu et al “Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology”. This paper details a circuit sensor design to measure and separate NBTI and positive bias temperature instability (PBTI) effects. The sensor can measure BTI degradation at the circuit infant stage rather than after manufacturing test to give high accuracy. And last the soft error highlighted presentation is by Lee et al titled “Radiation-Induced Soft Error Rate Analyses for 14 nm FinFET SRAM Devices”. This paper has a detailed study of soft errors due to high energy cosmic ray neutrons, alpha particles, and thermal neutrons at multiple planar CMOS process nodes, and the 14 nm FinFET node.  Transitioning to FinFETs greatly improves the soft error rate.  However, the thermal neutron soft error component decreases less than the high energy cosmic ray neutron and alpha particle components, so thermal neutrons become a larger contributor at 14 nm.

Please take advantage of registration now for lower conference fee and follow on Facebook, Linked-IN, Twitter @IEEEIRPS, visit for latest information. We look forward to seeing you in Monterey!

Chris Connor
2015 IRPS Vice Technical Program and Publicity Chair

Yuan Chen
2015 IRPS Technical Program Chair

Giuseppe LaRosa
2015 IRPS General Chair